ICS843N3960I Datasheet, PDF (10/20 Pages) Integrated Device Technology – Fourth Generation FemtoClock

ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both V_SWING and V_OH must meet the V_PP and V_CMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. If the driver is from another vendor, use their
termination recommendation.
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
CLK
nCLK
Differential
R1
R2
84Ω
84Ω
Input
Figure 2A. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
3.3V
3.3V
*R3
33Ω
Zo = 50Ω
Zo = 50Ω
*R4
33Ω
HCSL
R1
50Ω
*Optional – R3 and R4 can be 0Ω
CLK
nCLK
R2
50Ω
Differential
Input
Figure 2C. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 2D. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
10
©2012 Integrated Device Technology, Inc.