ICS843N3960I Datasheet, PDF (1/20 Pages) Integrated Device Technology – Fourth Generation FemtoClock

FemtoClock^® NG Crystal-to-3.3V LVPECL
Clock Generator
ICS843N3960I
DATA SHEET
General Description
The ICS843N3960I is a LVPECL Clock Synthesizer. The
ICS843N3960I can synthesize 100MHz, 125MHz, 156.25MHz and
212.5MHz from a single 25MHz crystal or reference clock.
Utilizing an external loop filter capacitor, the ICS843N3960I is
capable of holdover mode when the main reference clock becomes
unstable, making this ideal for redundant timing applications.
Features
• Fourth Generation FemtoClock® NG PLL technology
• Two differential LVPECL outputs
• Crystal oscillator interface designed for 12pF, 25MHz parallel
resonant crystal
• CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
• RMS phase jitter at 100MHz (12kHz – 20MHz): 0.510ps (max.)
• RMS phase jitter at 125MHz (12kHz – 20MHz): 0.575ps (max.)
• RMS phase jitter at 156.25MHz (12kHz – 20MHz):
0.504ps (max.)
• RMS phase jitter at 212.5MHz (12kHz – 20MHz): 0.512ps (max.)
• 3.3V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
OE ^Pullup
CLK_ SEL ^Pulldown
XTAL_IN
Xtal
25 MHz
Osc.
XTAL_OUT
CLK ^Pullup
25MHz
nCLK
Pullup /
Pulldown
0
LOR
Phase
Detector
1
+
Charge
FemtoClock NG
VCO
/N
Pump
/M
FSEL ^{_0 Pulldown}
FSEL ^{_1 Pulldown}
Divider
Control
Logic
Pin Assignment
FSEL_0 1 20 VCC
FSEL_1 2
19 VCCA
LOR
OE 3
18 VCC
Q1 4 17 Q0
nQ1 5 16 nQ0
V_EE 6
CP 7
15 LOR
14 VEE
V_EE 8 13 CLK_SEL
Q0
nCLK 9 12 XTAL_IN
nQ0
CLK 10 11 XTAL_OUT
Q1
nQ1
ICS843N3960I
20 Lead TSSOP, E-Pad
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
1
©2012 Integrated Device Technology, Inc.