ICS843N3960I Datasheet, PDF (13/20 Pages) Integrated Device Technology – Fourth Generation FemtoClock

ICS843N3960I Data Sheet
Schematic Example
Figure 5 shows an example ICS843N3960I application schematic.
Input and output terminations shown are intended as examples only
and may not represent the exact user configuration. Load caps C1 =
C2 = 4pF are recommended for frequency accuracy, but these may
be adjusted for different board layouts. If different crystal types are
used, please consult IDT for recommendations.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1uF capacitors be placed on the device side
of the PCB as close to the power pins as possible. This is
represented by the placement of these capacitors in the schematic.
If space is limited, the ferrite bead, 10uf and 0.1uF capacitors
connected to 3.3V can be placed on the opposite side of the PCB. If
space permits, place all filter components on the device side of the
board. Power supply filter recommendations are a general guideline
to be used for reducing external noise from coupling into the devices.
The filter performance is designed for a wide range of noise
frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set. If AC coupling for PECL levels is required to the CLK, nCLK
and/or Q0 and Q1 outputs, please refer to the IDT application note,
Termination - 3.3V PECL
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843N3960I provides
separate VCC and VCCA power supplies to isolate any high
switching noise from coupling into the internal PLL.
3. 3V
FB1
1
2
B LM18BB2 21SN 1
C1
0. 1uF
0 .1u F
C3
VC C
C2
U1
10u F
0. 1uF
C4
R1
10
10uF
C6
C5
0. 1uF
R2
33 0
FSEL _0
FSEL _1
OE
C LK_ SEL
1
2 ^{FSEL _0}
3 ^{FSEL _1}
13 OE
C LK_ SEL
15
L OR
7
CP
C9
2 5MH z (1 2pf )
12
XTA L_I N
11
XTA L_OU T
10uF
X1
C7
C8
4pF
4 pF
17
Q0
16
nQ0
3 .3 V
R3
13 3
Zo = 50 Ohm
Zo = 50 Ohm
R5
82. 5
R4
133
+
-
PEC L R ece iv e r
R6
82. 5
Zo = 50 Ohm
Zo = 50 Ohm
LVD S D riv er
R10
10
C LK
1 00
9
nC LK
Logic Control Input Examples
Set Logic
Set Logic
VC C _{Input to '1'} VC C _{Input to '0'}
RU1
1K
To Logic
Input
pins
RD1
N ot I nst all
RU2
N ot Ins tall
To Logic
In put
pins
RD2
1K
4
Q1
5
nQ1
Optional Four Resistor Thevinin Termination
Zo = 50 Ohm
Zo = 50 Ohm
+
-
P EC L R e ceiv er
R7
R8
50
50
R9
50
For AC termination options consult the IDTApplications Note
"Termination - 3.3V LVPECL"
Figure 5. ICS843N3960I Application Schematic
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
13
©2012 Integrated Device Technology, Inc.