ICS844N255I Datasheet, PDF (17/21 Pages) Integrated Device Technology – Six differential LVDS clock outputs

ICS844N255I Data Sheet
FEMTOCLOCK^® NG CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844N255I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844N255I is the sum of the core power plus the analog power plus the power dissipation in the load(s).
The following is the power dissipation for V_DD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
• Power (core)_MAX = V_{DD_MAX} * (I_{DD_MAX} + I_{DDA_MAX}) = 2.625V * (140mA + 24mA) = 430.5mW
• Power (outputs)_MAX = V_{DDO_MAX} * I_{DDO_MAX} = 2.625V * 111mA = 291.375mW
Total Power__MAX = 430.5mW + 291.375mW = 721.875mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow of
and a multi-layer board, the appropriate value is 29°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.722W * 29°C/W = 105.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θ_JA for 48 Lead VFQFN, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
29.0°C/W
1
25.4°C/W
2.5
22.8°C/W
ICS844N255AKILF REVISION A NOVEMBER 23, 2011
17
©2011 Integrated Device Technology, Inc.