ICS844N255I Datasheet, PDF (12/21 Pages) Integrated Device Technology – Six differential LVDS clock outputs

ICS844N255I Data Sheet
FEMTOCLOCK^® NG CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Applications Information
Interface to IDT SRIO Switches
The ICS844N255I is designed for driving the differential reference
clock input (REF_CLK) of IDT’s SRIO 1.3 and 2.0 switch devices. The
LVDS outputs of the ICS844N255I have the low-jitter, differential
voltage and impedance characteristics required to provide a
high-quality 156.25MHz clock signal for both SRIO 1.3 and 2.0 switch
devices. Please refer to Figure 1 for a suggested interfaces. In Figure
1, the AC-coupling capacitors are mandatory by the IDT SRIO switch
devices. The differential REF_CLK input is internally re-biased and
AC-terminated. The interface circuit is optimized for 50Ω
transmission lines and generates the voltage swing required to
reliably drive the clock reference input of a IDT SRIO switch. Please
refer to IDT’s SRIO device datasheet for more details.
Figure 1 shows the recommended interface circuit for driving the
156.25MHz reference clock of an IDT SRIO 2.0 switch by a LVDS
output of the ICS844N255I. The LVDS-to-differential interface as
shown in Figure 1 does not require any external termination resistors:
the ICS844N255I driver contains an internal source termination at
QA0 and QA1. The differential REF_CLK input contains an internal
AC-termination (R_L) and re-bias (V_BIAS).
QAn
LVDS nQAn
REF_CLK_P _LI
C_I
T= 50
V_BIAS
L_I
REF_CLK_N
C_I
R_{L + REF_CLK}
-
R_L
ICS844N255I
IDT SRIO 1.3, 2.0 Switch
Figure 1. LVDS-to-SRIO 2.0 Reference Clock Interface
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the REF_CLK to ground.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
ICS844N255AKILF REVISION A NOVEMBER 23, 2011
12
©2011 Integrated Device Technology, Inc.