ICS844N255I Datasheet, PDF (10/21 Pages) Integrated Device Technology – Six differential LVDS clock outputs

ICS844N255I Data Sheet
Parameter Measurement Information
FEMTOCLOCK^® NG CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
3.3V±5%
POWER SUPPLY
+ Float GND –
V_DD,
V_DDOX
V_DDA
LVDS
SCOPE
Qx
nQx
LVDS Output Load AC Test Circuit
Phase Noise Plot
f₁ ^{Offset Frequency} f₂
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter
nQX
QX
tcycle n
➤
tcycle n+1
➤
| | ^{tjit(cc) =} tcycle n – tcycle n+1
1000 Cycles
nQB0
QB0
nQB1
QB1
t sk(b)
Cycle-to-Cycle Jitter
Bank Skew
nQx
Qx
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Output Duty Cycle/Pulse Width/Period
nQx
20%
Qx
80%
t_R
Output Rise/Fall Time
80%
t_F
V_OD
20%
ICS844N255AKILF REVISION A NOVEMBER 23, 2011
10
©2011 Integrated Device Technology, Inc.