ICS844N255I Datasheet, PDF (16/21 Pages) Integrated Device Technology – Six differential LVDS clock outputs

ICS844N255I Data Sheet
Schematic Layout
Figure 5 shows an example of ICS844N255I application schematic.
In this example, the device is operated at V_DD = V_DDOA = V_DDOB =
V_DDOC = V_DDOD = V_DDOE = 2.5V. The 16pF parallel resonant 25MHz
crystal is used. The load capacitance C1 = 15pF and C2 = 15pF are
recommended for frequency accuracy. Depending on the parasitics
of the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. For this device, the
crystal load capacitors are required for proper operation.
FEMTOCLOCK^® NG CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS844N255I provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
XTAL_OU T
16 p F
C2
1 5p F
X1
25MH z
XTAL_I N
C1
1 5p F
Q1
R4 ₃₃
Zo = 50
R EF_C LK
R EF _S EL
MS EL
R1
VD D
V DD A
VD D
5 -10
C 3 0.1uF C 4 10uF
LVC MOS_Driv er
Logic Input Pin Examples
VD D O
QA
nQA
n O EA
n O EB
VD D O
Q B0
n Q B0
Q B1
n Q B1
Set Logic
Set Logic
V DD _{Input to '1'} V DD _{Input to '0'}
U1
1
2 ^GND
3 ^{VD D OA}
4 ^QA
5 ^nQA
6 ^{GND A}
7 ^{nOE A}
8 ^{nOE B}
9 ^{VD D OB}
10 ^QB0
11 ^{nQB 0}
12 ^QB1
nQB 1
36
GND ₃₅
VD D A ₃₄
VD D ₃₃
nOE E ₃₂
VD D OE ₃₁
QE ₃₀
nQE ₂₉
GNDE ₂₈
FS ELE ₂₇
V DD OD ₂₆
QD ₂₅
nQD
QA
+
Zo_D if f = 100 Ohm R 5
10 0
nQA
-
VD D
nOE E
VD D O
QE
n QE
FSE LE
VD D O
QD
n QD
LVDS Terminat ion
VDD=2.5V
VDDOA=VDDOB=VDDOC=2.5V
VDDOD=VDDOE=2.5V
QE
RU1
1K
To Logic
Input
pins
RD1
N ot I nst all
RU2
N ot I nst all
To Logic
Input
pins
RD2
1K
FSEL B
QC
n QC
2. 5V
muR ata, B LM18BB221S N 1
1
2 (U1:21) (U1:34) (U1:40) (U1:41) (U1:43)
F B3
C10
0. 1uF
C11
C12
10uF 0.1uF
C 21
C20
10uF 0. 1uF
C22
0 .1 u F
nOE D
FS ELD
F SELC
n O EC
VD D
VD D OC
V DD
R6
Zo_D if f = 100 Ohm 50
+
C5
0. 1uF
-
R7
50
nQ E
Alternat e
LVDS
Termination
2. 5V
muR ata, B LM18BB221S N 1
1
2
(U1:2) (U1:8) (U1:18) (U1:27) (U1:32) VD D O
F B2
C13
0. 1uF
C14
C15
10uF 0.1uF
C 16
0. 1uF
C17
0. 1uF
C18
0. 1uF
C1 9
0. 1uF
Figure 5. ICS844N255I Application Schematic
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
ICS844N255AKILF REVISION A NOVEMBER 23, 2011
16
©2011 Integrated Device Technology, Inc.