ICSSSTUBF32866A Datasheet, PDF (9/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUBF32866A
Advance Information
2. Device standard (cont'd)
G2
RST
CK ^H1
J1
CK
D1•D6,
D8-D13
V _REF
11
A3, T3
G5
C1
G1
P AR_IN
LPS0
(internal node)
D ^CE
CK Q
R
11
D1•D6,
D8•D13
Parity
Generator
D1•D6,
D8•D13
11
0
DQ
1
CK
R
DQ
CK
R
CE
1
D Q0
CK
R
11 _{Q1A•Q6A,}
Q8A•Q13A
11 _{Q1B•Q6B,}
Q8B•Q13B
A2
PPO
D2
QERR
G6
C0
CK
2•Bit
Counter
R
LPS1
(internal node)
0
D
Q
1
CK
R
Figure 8 Parity logic diagram for 1:2 register-B configuration (positive logic); CO=1, C1=1
1240—07/17/06
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