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ICSSSTUBF32866A Datasheet, PDF (15/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2 | |||
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ICSSSTUBF32866A
Advance Information
2. Device standard (cont'd)
RST#
DCS# â
tinact
CSR# â
CK â
CK# â
D1â¢D14 â
Q1â¢Q14
tRPHL
RST# to Q
PAR_IN â
PPO
tRPHL
RST# to PPO
QERR#
(not used)
tRPLH
RST# to QERR#
H, L, or X
H or L
Figure 14 â Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST# switches from H to L
â
After RST# is switched from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a
minimum time of tINACT max
1240â07/17/06
15
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