ICSSSTUBF32866A Datasheet, PDF (6/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUBF32866A
Advance Information
Block Diagram for 1:2 mode (positive logic)
RST
CK
CK
V_REF
DCKE
DODT
DCS
CSR
1D
C1
R
1D
C1
R
1D
C1
R
QCKEA
QCKE B*
QODTA
QODTB*
QCSA
QCSB*
1240—07/17/06
D1
0
1
To 10 Other Channels
*Note: Disabled in 1:1 configuration
1D
C1
R
6
Q1A
Q1B^*