ICSSSTUBF32866A Datasheet, PDF (17/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUBF32866A
Advance Information
2. Device standard (cont'd)
RST#
DCS#
CSR#
CK
n
n+1
n+2
n+3
n+4
CK#
D1•D14
Q1•Q14
P AR_IN
PPO
QERR# ^†
(not used)
tsu
th
tpdm , t _pdmss
CK to Q
tsu
th
tpd
CK to PPO
Data to PPO
Latency
Data to QERR#
Latency
tPHL or t _PLH
CK to QERR#
Unknown input
event
Output signal is dependent on
the prior unknown input event
H or L
Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B cofiguration) device used in
pair; C0=1, C1=1; RST# being held high
†
PAR_IN is driven from PPO of the first SSTU32866 device
‡
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an erro occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
1240—07/17/06
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