ICSSSTUBF32866A Datasheet, PDF (1/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

Integrated
Circuit
Systems, Inc.
ICSSSTUBF32866A
Advance Information
25-Bit Configurable Registered Buffer for DDR2
Recommended Application:
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS97ULP877
• Ideal for DDR2 667, and 800
Product Features:
• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity check functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on CSR and
RESET inputs
• Low voltage operation
V_DD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages available
Functionality Truth Table
I nputs
Outp uts
RST
DCS
CSR
CK
Dn,
CK DODT, Qn
DCK E
QCS
QODT,
QCKE
H
L
L
L
L
L
L
H
L
L
H
H
L
H
H
L
L
L or H L or H
X
Q₀
Q₀
Q₀
H
L
H
L
L
L
L
H
L
H
H
H
L
H
H
L
H
L or H L or H
X
Q₀
Q₀
Q₀
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L or H L or H
X
Q₀
Q₀
Q₀
H
H
H
L
Q₀
H
L
H
H
H
H
Q₀
H
H
H
H
H
L or H L or H
X
Q₀
Q₀
Q₀
L
X or
X or
X or
X or
X or
Floating Floating Floating Floating Floating
L
L
L
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96 Ball BGA
(Top View)
1240—07/17/06
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.