ICSSSTUBF32866A Datasheet, PDF (21/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUBF32866A
Advance Information
Electrical Characteristics - DC
T_A = 0 - 70°C; V_DD = 1.8 +/-0.1V (unless otherwise stated)
SYMBOL PARAMETERS
CONDITIONS
V_IK
I_I = -18mA
V_OH
I_OH = -6mA
V_OL
I_OL = 6mA
I_I All Inputs
Standby (Static)
V_I = V_DD or GND
RESET# = GND
I_DD
Operating (Static)
V_I = V_IH(AC) or V_IL(AC),
RESET# = V_DD
RESET# = V_DD,
Dynamic operating
(clock only)
V_I = V_IH(AC) or V_IL(AC),
CLK and CLK# switching
50% duty cycle.
Dynamic Operating ^{RESET# = VDD,}
I_{DDD (per each data input) VI = VIH(AC) or VIL (AC),}
I_O = 0
1:1 mode
CLK and CLK# switching
50% duty cycle. One data
Dynamic Operating _{input switching at half}
(per each data input) _{clock frequency, 50%}
1:2 mode
duty cycle
Data Inputs
C_i CLK and CLK#
RESET#
V_I = V_REF ±350mV
V_ICR = 1.25V, V_I(PP) = 360mV
V_I = V_DD or GND
Notes:
1 - Guaranteed by design, not 100% tested in production.
V_DD
1.7V
1.7V
1.9V
1.9V
1.8V
MIN TYP MAX
-1.2
1.2
0.5
-5
5
100
40
UNITS
V
µA
µA
mA
39
µ/clock
MHz
19
µA/ clock
MHz/data
35
2.5
3.5
pF
2
3
2.5
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
PARAMETER
V_DD = 1.8V ± 0.1V
MIN
MAX
UNIT
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
dV/dt_∆¹
1
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1240—07/17/06
21