ICSSSTUBF32866A Datasheet, PDF (22/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUBF32866A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
f_clock
t_W
Clock frequency
Pulse duration, CK, CK HIGH or LOW
VDD = 1.8V ±0.1V
MIN MAX
-
410
1
-
t_ACT Differential inputs active time (See Notes 1 and 2)
-
10
t_INACT
t_su
Differential inputs inactive time (See Notes 1 and 3)
Setup time
t_su Setup time
t_su Setup time
t_su Setup time
-
15
DCS# before CK↑, CK#↓,
0.55
CSR# high
CSR# before CK↑, CK#↓,
0.55
DCS# high
DCS# before CK↑, CK#↓,
0.35
CSR# low
DODT, DCKE and data before
CK↑, CK#↓
0.35
t_su Setup time
PAR_IN before CK↑, CK#↓
0.35
Hold time
t_H
Hold time
DCS#, DODT, DCKE and Q
after CK↑, CK#↓
0.35
PAR_IN after CK↑, CK#↓
0.35
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN MAX
fmax Max input clock frequency
410
t_PDM
Propagation delay, single _{CK↑ to CK#↓ QN}
bit switching
1.1
1.5
t_PD Propagation delay
CK↑ to CK#↓ to PPO
0.5
1.7
t_LH
Low to High propagation _{CK↑ to CK#↓ to QERR#}
delay
1.2
3
t_HL
High to low propagation
delay
CK↑ to CK#↓ to QERR#
1
2.4
t_PDMSS
Propagation delay
simultaneous switching
CK↑ to CK#↓ QN
-
1.6
t_PHL
High to low propagation
delay
Rst# ↓ to QN↓
3
t_PHL
High to low propagation
delay
Rst# ↓ to PPO↓
3
t_PLH
Low to High propagation
delay
Rst# ↓ to QERR#↑
3
2. Guaranteed by design, not 100% tested in production.
1240—07/17/06
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
22