ICSSSTUA32S869B Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – 14-Bit Configurable Registered Buffer for DDR2

ICSSSTUA32S869B
Advance Information
Register Timing
RESET#
DCS#
CSR#
CLK
CLK#
D1 - D4⁽¹⁾
Q1 - Q14⁽¹⁾
PAR_IN1,⁽²⁾
PAR_IN2
PPO1, ⁽²⁾
PPO2
(not used)
PTYERR1#, ⁽²⁾
PTYERR2#
n
n+1
n+2
tsu
tH
tPD
CLK to Q
tSU
tH
tPD
CLK to PPO
tPD
CLK to PTYERR#
Note 1: This range doesn't include D1, D4 and D7 and their corresponding outputs
n+3
n+4
tPD
CLK to PTYERR#
1173—10/28/05
9