ICSSSTUA32S869B Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – 14-Bit Configurable Registered Buffer for DDR2

ICSSSTUA32S869B
Advance Information
Terminal Functions
Signal Group Signal Name
Ungated inputs DCKE, DODT
Chip Select
gated inputs
D1 ... D14⁽¹⁾
Chip Select
inputs
DCS#, CSR#
Type
SSTL_18
SSTL_18
SSTL_18
Re-driven
outputs
Parity input
Q1A...Q14A,
SSTL_18
Q1B ... Q14B,
QCSA#, QCSB#
QCKEA,QCKEB
QODTA,QODTB
PARIN1
SSTL_18
Parity output _PPO1
SSTL_18
Description
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
DRAM Chip Select signals. This pins initiate DRAM address/
command decodes, and as such at least one will be low when
a valid address/command is present.
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
Inout parity is received on pin PARIN1 and should maintain
parity across the D1...D14⁽¹⁾ inputs, at the rising edge of the
clock, one cycle after Chip Select is LOW.
Partial Parity Output. Indicates parity out of D1-D14⁽¹⁾
Parity error
output
PTYERR1#
Open drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR1# will be active for two clock cycles, and delayed
by in total 2 clock cycles for compatibility with final parity
out timing on the industry-standard DDR2 register with
parity (in JEDEC definition).
Configuration C1
Inputs
1.8V
LVCMOS
When Low, register is configured as Register 1. When High,
register is confugured as Register 2.
Clock inputs CK, CK#
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Miscellaneous RESET#
inputs
1.8 V
LVCMOS
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET#
also resets the PTYERR# signal.
VREF
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
VDD
Power Input Power supply voltage
GND
Ground Input Ground
NOTE 1 Inputs D1, D4 and D7 and their corresponding outputs Qn are not included in this range.
1173—10/28/05
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