ICSSSTUA32S869B Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – 14-Bit Configurable Registered Buffer for DDR2

ICSSSTUA32S869B
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD = 1.8V ±0.1V
MIN MAX
f_clock
t_ACT
t_INACT
t_S
Clock frequency
Differential inputs active time
Differential inputs inactive time
Setup time
Data before CLK↑, CLK#↓
DCS0 before CLK↑, CLK#↓,
CSR# high
340
10
15
0.5
0.7
Hold time
t_H
Hold time
DCS#, DODT, DCKE and Q
after CK↑, CK#↓
0.30
PARIN1 after CK↑, CK#↓
0.30
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
UNITS
MHz
ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN MAX
fmax Max input clock frequency
340
t_PDM
Propagation delay, single _{CK↑ to CK#↓ QN}
bit switching
t_LH
Low to High propagation CK↑ to CK#↓ to
delay
PTYERR#
t_HL
High to low propagation
delay
CK↑ to CK#↓ to
PTYERR#
t_PDMSS
Propagation delay
simultaneous switching
CK↑ to CK#↓ QN
t_PHL
High to low propagation
delay
RESET# ↓ to QN↓
Low to High propagation RESET# ↓ to
t_{PLH delay}
PTYERR1#↑
1. Guaranteed by design, not 100% tested in production.
1.2
1.9
1.2
3
1
3
2
3
3
Units
MHz
ns
ns
ns
ns
ns
ns
1173—10/28/05
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