ICSSSTUA32S869B Datasheet, PDF (15/18 Pages) Integrated Circuit Systems – 14-Bit Configurable Registered Buffer for DDR2

ICSSSTUA32S869B
Advance Information
Error output load circuit and voltage measurement information (V_DD = 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR10 MHz;
Z_o = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
VDD
DUT
RL = 1 k
OUT
TEST POINT
CL = 10 pF
SEE NOTE (1)
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(1) C_L includes probe and jig capacitance.
Figure 16 — Load circuit, error output measurements
LVCMOS
RESET
Input
tPLH
VCC/2
VCC
0V
VOH
Output
Waveform 2
0.15 V
0V
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Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET#
input
Timing
Inputs
VICR
VICR
VI(PP)
tHL
Output
Waveform 1
VCC/2
VCC
VOL
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Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock
inputs
Timing
Inputs
VICR
VICR
VI(PP)
tLH
Output
Waveform 2
0.15 V
VOH
0V
002aaa503
Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock
inputs
1173—10/28/05
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