ICSSSTUA32S869B Datasheet, PDF (3/18 Pages) Integrated Circuit Systems – 14-Bit Configurable Registered Buffer for DDR2

ICSSSTUA32S869B
Advance Information
Parity and Standby Function Table
RESET#
H
H
H
H
H
H
H
H
H
H
L
DCS#
L
L
L
L
L
L
L
L
H
X
X or
floating
CSR#
X
X
X
X
L
L
L
L
H
X
X or
floating
Inputs
CK
CK#
↑
↑
↑
↑
↑
↑
↑
↑
↑
L or H
X or
floating
↓
↓
↓
↓
↓
↓
↓
↓
↓
L or H
X or
floating
£ of inputs = H
D1..…D14⁽¹⁾
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
X
X or
floating
PARIN1⁽²⁾
L
L
H
H
L
L
H
H
X
X
X or
floating
Output
PPO1⁽²⁾ PTYERR1#⁽³⁾
L
H
H
L
L
H
H
L
PPOn₀
PPOn₀
L
H
L
L
H
H
L
L
H
PTYERRn₀#
PTYERRn₀#
H
NOTE 1
NOTE 2
NOTE 3
Inputs D1, D4 and D4 are not included in this range.
PARIN1 arrives one (C1 = 0) or two (C = 1) clock cycles after data to which it applies.
This transition assumes PTYERR1# is high at the crossing of CK going high and CK# going low.
If PTYERR1# is low, it stays latched low for two clock cycles or until RESET# is driven low. PARIN1 is
used to generate PPO1 and PTYERR1#.
1173—10/28/05
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