ICS9FG1904B-1 Datasheet, PDF (9/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Electrical Characteristics - Skew and Differential Jitter Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
Group
Parameter
Description
CLK_IN, DIF[x:0]
t_{SPO_PLL}
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25°C, 3.3V
CLK_IN, DIF[x:0]
t_{PD_BYP}
Input-to-Output Skew in Bypass mode (1:1 only),
nominal value @ 25°C, 3.3V
CLK_IN, DIF [x:0]
∆t_{SPO_PLL}
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating ranges)
Min Max Units Notes
-500 500 ps 1,2,4,5,8
2.5 4.5 ns 1,2,3,5
|350|
ps
1,2,4,5,6,
10
CLK_IN, DIF [x:0]
∆t_{PD_BYP}
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
|500|
ps
1,2,3,4,5,
6,10
DIF[14:0]
DIF[18:15]
DIF[18:0]
DIF[18:0]
t_{SKEW_G15}
tSKEW_G4
t_{SKEW_A19}
t_JPH
Output-to-Output Skew Group of 15
(Common to Bypass and PLL mode)
Output-to-Output Skew Group of 4 (Common to Bypass and PLL
mode)
Output-to-Output Skew across all 19 outputs
(Common to Bypass and PLL mode - all outputs at same gear)
Differential Phase Jitter (RMS Value)
100 ps
1,2
50 ps
1.2
150 ps
10 ps
1,2,3
1,4,7
DIF[18:0]
t_SSTERROR Differential Spread Spectrum Tracking Error (peak to peak)
80 ps 1,4,9
NOTES:
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate ICS9FG1900 devices driven by a single CK410B. The ICS9FG1900's must be set to high
bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target
ranges of consideration are agents with BW of 1-22Mhz and 11-33Mhz.
8. t is the period of the input clock
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two ICS9FG1900 devices This parameter is measured at
the outputs of two separate ICS9FG1900 devices driven by a single CK410B in Spread Spectrum mode. The ICS9FG1900's must be set to high bandwidth.
The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear profile.
10. This parameter is an absolute value. It is not a double-sided figure.
Electrical Characteristics - Phase Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, when driven by 932S421B or equivalent
PARAMETER
Symbol
Conditions
Min
Typ
t_jphPCIe1
PCIe Gen 1
t_jphPCIe2Lo
PCIe Gen 2
10kHz < f < 1.5MHz
Jitter, Phase
PCIe Gen 2
t_{jphPCIe2Hi 1.5MHz < f < Nyquist (50MHz)}
t_{jphFBD1_3.2G}
FBD1 3.2/4G
11MHz to 33MHz
t_{jphFBD1_4.0G}
FBD1 4.8G
11MHz to 33MHz
Notes:
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See http://www.pcisig.com for complete specs}
Max
108
3
Units Notes
ps (p-p) 1,2
ps (RMS) 1,2
3.1 ps (RMS) 1,2
3 ps (RMS) 1,2
2.5 ps (RMS) 1,2
1255B—08/03/07
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