ICS9FG1904B-1 Datasheet, PDF (17/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBusTable: Control Pin Readback Register
Byte 8 Pin #
Name
Control Function
Bit 7
5
Readback - FS_A_410
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
DIF_18
Output Control
Bit 3
DIF_17
Output Control
Bit 2
DIF_16
Output Control
Bit 1
DIF_15
Output Control
Bit 0
DIF_14
Output Control
Type
R
RW
RW
RW
RW
RW
0
1
Readback
Hi-Z
Enable
Hi-Z
Enable
Hi-Z
Enable
Hi-Z
Enable
Hi-Z
Enable
PWD
X
X
X
1
1
1
1
1
SMBusTable: 1:1 PLL Operating Set Point Register
Byte 9 Pin #
Name
Control Function
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
RESERVED
Bit 2
-
Frequency Select C
Bit 1
-
Frequency Select B
Bit 0
-
FS_A_410
Type
0
1
PWD
0
0
0
0
0
RW
x
RW See ICS9FG1904 1:1 1
PLL Programming Table
RW
Latch
SMBus Table: M/N Programming & Watchdog Safe Register
Byte 10 Pin #
Name
Control Function
Bit 7
-
M/N_EN
Gear and 1:1 PLL M/N
Programming Enable
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
RESERVED
Bit 2
RESERVED
Bit 1
RESERVED
Bit 0
RESERVED
Type
RW
0
Disable
1
Enable
PWD
0
X
X
X
X
X
X
X
SMBus Table: Gear PLL Frequency Control Register
Byte 11 Pin #
Name
Control Function
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
-
Gear PLL M Div5
Bit 4
-
Gear PLL M Div4
Bit 3
-
Bit 2
-
Gear PLL M Div3
Gear PLL M Div2
M Divider
Bit 1
-
Gear PLL M Div1
Bit 0
-
Gear PLL M Div0
Type
0
1
PWD
X
X
RW
X
RW
X
RW See M/N Programming Section X
RW
of the Data Sheet
X
RW
X
RW
X
1255B—08/03/07
17