ICS9FG1904B-1 Datasheet, PDF (10/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Programming the 9FG1904B-1
The 9FG1904B-1 uses advanced power saving features to detect when only geared outputs or only 1:1 outputs are
needed. It then shuts down the unused PLL. At power up all outputs are coming from the 1:1 PLL and the Gear PLL
is shut down. This power saving feature requires a little care when configuring the gear outputs in the device.
Configuring Gear Outputs of the 9FG1904B-1
Selecting Pre-configured Gear Ratios
Byte 0 contains both the bits that enable the gear ratio outputs (Bits 7 and 6), and the bits that select the actual gear
ratio (bits (4:0)). It is tempting to enable the gearing outputs and select the gear ratio at the same time. However, this
can result in the inability to obtain the proper output frequency. Due to the power saving feature, it is necessary to perform
this operation as two steps:
1. First, enable outputs to the gear ratio PLL, which actually powers up the gear ratio PLL (Set Byte 0, bits 7 and
6)
2. Then select the desired gear ratio in a separate write to byte 0 (Set Byte 0, bits (4:0)
The actual order of the two operations is unimportant, so steps 1 and 2 could be reversed if desired.
Programming Gear Ratios that are not Pre-Configured
Most applications using the 9FG1904B-1 can obtain the desired output frequencies from the selections built into the
gear table. There are two gear tables defined for these devices. There is the original GS gear set indicated by the
DBxxxxGS yellow cover designation and the newer optimized GSO gear set indicated by DBxxxxGSO yellow cover
designation. The 9FG1904B-1 contains a gear set that is a combination of the GS and GSO gear sets. The differences
between the GS and GSO gear sets are highlighted in Figure 1 GS versus GSO versus 9FG1904B-1 Gear Ratios.
Any gear in the GS or the GSO table that is not pre-configured in the 9FG1904B-1, and virtually any other input/output
combination can be obtained by use of M/N programming. Note that care must be used or the jitter/bandwidth
characteristics of the PLL can be compromised.
The values provided later in this document have been verified to preserve the PLL performance of the device. Refer
to the section Using M/N Programming to Obtain Other Gear Ratios for additional details.
1255B—08/03/07
10