ICS9FG1904B-1 Datasheet, PDF (2/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Pin Description
PIN #
PIN NAME
1 IREF
2 GNDA
3 VDDA
4 HIGH_BW#
5 FS_A_410
6 DIF_0
7 DIF_0#
8 DIF_1
9 DIF_1#
10 GND
11 VDD
12 DIF_2
13 DIF_2#
14 DIF_3
15 DIF_3#
16 DIF_4
17 DIF_4#
18 OE_01234#
19 SMBCLK
20 SMBDAT
21 OE5#
22 DIF_5
23 DIF_5#
24 OE6#
25 DIF_6
26 DIF_6#
27 VDD
28 GND
29 OE7#
30 DIF_7
31 DIF_7#
32 OE8#
33 DIF_8
34 DIF_8#
35 SMB_A0
36 SMB_A1
PIN TYPE
DESCRIPTION
This pin establishes the reference current for the differential current-mode
OUT output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
PWR Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
3.3V tolerant low threshold input for CPU frequency selection. This pin
IN
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and
Vih_FS threshold values.
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
PWR Ground pin.
PWR Power supply, nominal 3.3V
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
IN
Clock pin of SMBUS circuitry, 5V tolerant
I/O Data pin of SMBUS circuitry, 5V tolerant
IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
PWR Power supply, nominal 3.3V
PWR Ground pin.
IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN
SMBus address bit 0 (LSB)
IN
SMBus address bit 1
1255B—08/03/07
2