ICS9FG1904B-1 Datasheet, PDF (7/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
Absolute Max
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
SYMBOL
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
ICS9FG1904B-1
CONDITIONS
Human Body Model
MIN
GND - 0.5
GND - 0.5
-65
0
2000
TYP
MAX UNITS
V_DD + 0.5V V
V_DD + 0.5V V
150
°_C
70
°C
115
°C
V
Notes
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V_IH
3.3 V +/-5%
Input Low Voltage
Input High Current
Input Low Current
V_IL
3.3 V +/-5%
I_IH
V_IN = V_DD
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
MIN
2
V_SS - 0.3
-5
-5
TYP
Low Threshold Input-
High Voltage
V_{IH_FS}
3.3 V +/-5%, Applies to FS_A_410
pin
0.7
Low Threshold Input-
Low Voltage
Operating Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
V_OL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
V_{IL_FS}
3.3 V +/-5%, Applies to FS_A_410
pin
V_SS - 0.3
I_DD3.3OP
all outputs driven
I_DD3.3PD
all differential pairs tri-stated
F_i
V_DD = 3.3 V
100
L_pin
C_IN
Logic Inputs
C_OUT
Output pin capacitance
2.5
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
30
DIF output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
V_MAX
Maximum input voltage
V_OL
@ I_PULLUP
I_PULLUP
4
T_RI2C
T_FI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
MAX
V_DD + 0.3
0.8
5
UNITS
V
V
uA
uA
V_DD + 0.3 V
0.35
V
500
mA
30
mA
400
MHz
7
nH
5
pF
pF
1.8
ms
33
kHz
300
us
5
ns
5
ns
5.5
V
0.4
V
mA
1000
ns
300
ns
Notes
1
1
1
1
1
1
3
1
1
1
1
1
1
1
2
1
1
1
1
1
1255B—08/03/07
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