ICS932S422C Datasheet, PDF (8/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers

Integrated
Circuit
Systems, Inc.
ICS932S422C
Electrical Characteristics - SRC/SATA 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
Current Source Output Impedance
Zo
V_O = V_x
3000
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Average period
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
VHigh
VLow
Vovs
Vuds
Vx(abs)
d-Vx
ppm
Tperiod
Tabsmin
t_r
t_f
d-t_r
d-t_f
Statistical measurement on single ended
signal
Measurement on single ended signal
using absolute value.
Variation of crossing over all edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
V_OL = 0.175V, V_OH = 0.525V
V_OH = 0.525V V_OL = 0.175V
V_OL = 0.175V, V_OH = 0.525V
V_OH = 0.525V V_OL = 0.175V
660
-150
-300
250
-300
9.9970
9.9970
9.8720
175
175
Duty Cycle
d_t3
Measurement from differential wavefrom
45
Skew
t_sk3
V_T = 50%
Jitter, Cycle to cycle
t_jcyc-cyc Measurement from differential wavefrom
*T_A = 0 - 70°C; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33.2Ω, R_P=49.9Ω, Ι_REF = 475Ω
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz}
3_{IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.}
MAX
850
150
1150
550
140
300
10.0030
10.0533
525
525
125
125
55
250
125
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS*
MIN
Output Impedance
R_DSP
V_O = V_DD*(0.5)
12
Output High Voltage
V_OH
I_OH = -1 mA
2.4
Output Low Voltage
V_OL
I_OL = 1 mA
Output High Current
I_OH
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
-33
Output Low Current
I_OL
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
30
Rise Time
t_r
V_OL = 0.4 V, V_OH = 2.4 V
0.5
Fall Time
t_f
V_OH = 2.4 V, V_OL = 0.4 V
0.5
Duty Cycle
d_t1
V_T = 1.5 V
45
Group Skew
t_skew
V_T = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified)
1_{Guaranteed by design and characterization, not 100% tested in production.}
3 _{Spread Spectrum is off}
TYP
MAX
55
0.55
-33
38
2
2
55
250
500
UNITS
Ω
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ns
ps
ps
ps
ps
%
ps
ps
Notes
1
1,3
1,3
1
1
1
1
1,2
2
2
1,2
1
1
1
1
1
1
1
UNITS
Ω
V
V
mA
mA
mA
mA
ns
ns
%
ps
ps
NOTES
1
1
1
1
1
1
1
1
1
1
1
1
1412A—12/10/07
8