ICS932S422C Datasheet, PDF (16/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers

Integrated
Circuit
Systems, Inc.
ICS932S422C
SMBus Table: CPU Programmable Output Divider Register
Byte 19
Pin #
Name
Control Function Type
Bit 7
-
CPUDiv3
RW
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
Bit 1
Bit 0
CPUDiv2
CPUDiv1
CPUDiv0
CPU Divider Ratio RW
Programming Bits
RW
RW
RESERVED
RESERVED
RESERVED
RESERVED
0
1
See CPU, SRC and PCI
Divider Ratios Table
PWD
X
X
X
X
X
X
X
X
SMBus Table: SRC and PCI Programmable Output Divider Register
Byte 20
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
PCIDiv3
PCIDiv2
PCIDiv1
PCIDiv0
SRC_Div3
SRC_Div2
SRC_Div1
SRC_Div0
Control Function
PCI Divider Ratio
Programming Bits
SRC_ Divider Ratio
Programming Bits
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See CPU, SRC and PCI
Divider Ratios Table
See CPU, SRC and PCI
Divider Ratios Table
PWD
X
X
X
X
X
X
X
X
SMBusTable: Test Byte Register
Byte 21
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Test
-
-
-
-
-
-
-
-
Test Function
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
Note: Do NOT write to Bit 21. Erratic device operation will result!
Type
RW
RW
RW
RW
RW
RW
RW
RW
Test Result
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
1412A—12/10/07
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