ICS932S422C Datasheet, PDF (13/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers

Integrated
Circuit
Systems, Inc.
ICS932S422C
SMBus Table: Byte Count Register
Byte 8
Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function Type
0
1
PWD
RW
0
RW
0
RW ^{Writing to this register will}
0
Byte Count Programming
b(7:0)
RW
RW
configure how many bytes will
be read back, default is 8
bytes.
0
1
RW
(0 to 7)
0
RW
0
RW
0
SMBus Table: Device ID Register
Byte 9
Pin #
Name
Bit 7
DID7
Bit 6
Bit 5
DID6
DID5
Bit 4
DID4
Bit 3
DID3
Bit 2
DID2
Bit 1
DID1
Bit 0
DID0
Control Function Type
0
R
-
R
-
R
-
Device ID
(0C hex)
R
-
R
-
R
-
R
-
R
-
1
PWD
-
0
-
0
-
0
-
0
-
1
-
1
-
0
-
0
SMBus Table: M/N Programming & Control Register
Byte 10
Bit 7
Bit 6
Bit 5
Pin #
-
-
CPU
Bit 4
SRC
Bit 3
SRC, PCI
Bit 2
Bit 1
Bit 0
CPU
54
55
Name
M/N_EN
Spread Spectrum
Enable
Spread Spectrum
Enable
SRC Alternate
Frequency (96% of
Nominal)
CPU Alternate
Frequency (96% of
Nominal) Only active if
latched frequency is
166 MHz or 333 MHz.
REF1 Drive Strength
REF0 Drive Strength
Control Function Type
CPU and SRC
RW
M/N Programming
RESERVED
Spread Off/On
RW
Spread Off/On
RW
Set SRC = 96 MHz and
PCI = 32 MHz
Only active if
RW
Byte 10, bit 2 = 1
Set alternate CPU
frequency:
166 MHz to 160 MHz
RW
333 MHz to 320 MHz
1X or 2X
RW
1X or 2X
RW
0
Disable
1
Enable
Spread Off
Spread Off
Spread On
Spread On
Normal
Alternate
Frequency
Normal
Alternate
Frequency
See REF Drive Strength
Functionality Table
PWD
0
0
0
0
0
0
1
1
1412A—12/10/07
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