ICS932S422C Datasheet, PDF (17/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers

Integrated
Circuit
Systems, Inc.
ICS932S422C
PD, Power Down
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
PD
CPU CPU # SRC SRC# PCIF/PCI USB
REF Note
1
Normal Normal Normal Normal 33MHz 48MHz 14.318MHz
1
0
Iref * 2 or Float Iref * 2 Float
Low
Low
Low
1
Float
or Float
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD Assertion
PD should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Byte 4 for additional information.
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
CPU, SRC and PCI Divider Ratios
Div(3:0)
Divider
0
0000
2
1
0001
3
2
0010
5
3
0011
15
4
0100
4
5
0101
6
6
0110
10
7
0111
30
8
1000
8
9
1001
12
10
1010
20
11
1011
60
12
1100
16
13
1101
24
14
1110
40
15
1111
120
1412A—12/10/07
REF Drive Strength Functionality
Byte6, Byte 10, Byte 10,
bit 4 bit 1
bit 0 REF1
0
X
X
1x
1
0
0
1x
1
0
1
1x
1
1
0
2x
1
1
1
2x
REF0
1x
1x
2x
1x
2x
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