ICS932S422C Datasheet, PDF (18/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers

Integrated
Circuit
Systems, Inc.
ICS932S422C
PD De-assertion
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD deassertion.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tstable
<1.8mS
Tdrive_PwrDwn#
<300µS, >200mV
Test Clarification Table
Comments
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input.
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B6b6.
If test mode is invoked by B6b6, only B6b7
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
HW
FSLC/TES
T_SEL
HW PIN
0
1
1
1
FSLB/TES
T_MODE
HW PIN
X
0
0
1
SW
TEST
ENTRY REF/N or
BIT
HI-Z
B6b6 B6b7 OUTPUT
0
X NORMAL
X
0
HI-Z
X
1
REF/N
X
0
REF/N
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
1412A—12/10/07
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