ICS932S422C Datasheet, PDF (6/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers

Integrated
Circuit
Systems, Inc.
ICS932S422C
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage
VDD_A
-
3.3V Logic Input Supply
Voltage
VDD_In
-
Storage Temperature
Ts
-
Ambient Operating Temp Tambient
-
Case Temperature
Tcase
-
Input ESD protection HBM ESD prot
-
1_{Guaranteed by design and characterization, not 100% tested in production.}
MIN
GND - 0.5
-65
0
2000
TYP
MAX
V_DD + 0.5V
V_DD + 0.5V
150
70
115
UNITS
V
V
°_C
°C
°C
V
Notes
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
V_SS - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
-5
V_DD + 0.3
V
1
0.8
V
1
5
uA
1
uA
1
I_IL2
V_IN = 0 V; Inputs with pull-up resistors -200
uA
1
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Supply Current
Operating Current
Powerdown Current
V_{IH_FS}
V_{IL_FS}
I_DD3.3OP
I_DD3.3OP
I_DD3.3PD
3.3 V +/-5%
3.3 V +/-5%
Full Active, C_L = Full load;
all outputs driven
all diff pairs driven
all differential pairs tri-stated
0.7
V_SS - 0.3
V_DD + 0.3
V
1
0.35
V
1
350
mA
1
400
mA
1
70
mA
1
12
mA
1
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD
Tfall_PD
F_i
V_DD = 3.3 V
14.31818
MHz
2
L_pin
7
nH
1
C_IN
Logic Inputs
5
pF
1
C_OUT
Output pin capacitance
6
pF
1
C_INX
T_STAB
X1 & X2 pins
From VDD Power-Up or de-assertion
of PD to 1st clock
5
pF
1
1.8
ms
1
Triangular Modulation
30
33
kHz
1
CPU output enable after
PD de-assertion
300
us
1
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.}
1412A—12/10/07
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