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ICS932S422C Datasheet, PDF (15/21 Pages) Integrated Circuit Systems – PCIe Gen 2 main Clock for Intel-based Servers
Integrated
Circuit
Systems, Inc.
ICS932S422C
SMBus Table: SRC Frequency Control Register
Byte 15
Pin #
Name
Control Function
Bit 7
-
SRC N Div8
N Divider Prog bit 8
Bit 6
-
SRC N Div9
N Divider Prog bit 9
Bit 5
-
Bit 4
-
SRC M Div5
SRC M Div4
Bit 3
-
Bit 2
-
SRC M Div3
SRC M Div2
M Divider Programming
bits
Bit 1
-
SRC M Div1
Bit 0
-
SRC M Div0
Type
0
1
PWD
RW The decimal representation of X
RW M and N Divider in Byte 15 and X
RW 16 will configure the SRC VCO X
RW frequency. Default at power X
RW up = latch-in or Byte 0 Rom X
RW table. VCO Frequency =
X
RW 14.318 x [NDiv(9:0)+8] /
X
RW
[MDiv(5:0)+2]
X
SMBus Table: SRC Frequency Control Register
Byte 16
Pin #
Name
Control Function
Bit 7
-
Bit 6
-
SRC N Div7
SRC N Div6
Bit 5
-
SRC N Div5
Bit 4
-
Bit 3
-
SRC N Div4
SRC N Div3
N Divider Programming
b(7:0)
Bit 2
-
SRC N Div2
Bit 1
-
SRC N Div1
Bit 0
-
SRC N Div0
Type
0
1
PWD
RW The decimal representation of X
RW M and N Divider in Byte 15 and X
RW 16 will configure the SRC VCO X
RW frequency. Default at power X
RW up = latch-in or Byte 0 Rom X
RW table. VCO Frequency =
X
RW 14.318 x [NDiv(9:0)+8] /
X
RW
[MDiv(5:0)+2]
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 17
Pin #
Name
Control Function
Bit 7
-
SRC SSP7
Bit 6
-
Bit 5
-
SRC SSP6
SRC SSP5
Bit 4
-
Bit 3
-
SRC SSP4
SRC SSP3
Spread Spectrum
Programming b(7:0)
Bit 2
-
Bit 1
-
SRC SSP2
SRC SSP1
Bit 0
-
SRC SSP0
Type
0
RW
1
PWD
X
RW
X
RW
X
RW
These Spread Spectrum bits in
Byte 17 and 18 will program
X
RW the spread pecentage of SRC X
RW
X
RW
X
RW
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 18
Pin #
Name
Control Function
Bit 7
-
Reserved
Reserved
Bit 6
-
SRC SSP14
Bit 5
-
SRC SSP13
Bit 4
-
Bit 3
-
Bit 2
-
SRC SSP12
SRC SSP11
SRC SSP10
Spread Spectrum
Programming b(14:8)
Bit 1
-
SRC SSP9
Bit 0
-
SRC SSP8
Type
0
R
-
1
PWD
-
0
RW
X
RW
X
RW These Spread Spectrum bits in X
RW Byte 17 and 18 will program X
RW the spread pecentage of SRC X
RW
X
RW
X
1412A—12/10/07
15