ICS8745B Datasheet, PDF (8/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLKx
nCLKx
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
LVDS_Driv er
3.3V
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
8745BY
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8
REV. B DECEMBER 2, 2004