ICS8745B Datasheet, PDF (3/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
0
0
0
0
250 - 700
0
0
0
1
125 - 350
0
0
1
0
62.5 - 175
0
0
1
1
31.25 - 87.5
0
1
0
0
250 - 700
0
1
0
1
125 - 350
0
1
1
0
62.5 - 175
0
1
1
1
250 -700
1
0
0
0
125 - 350
1
0
0
1
250 - 700
1
0
1
0
125 - 350
1
0
1
1
62.5 - 175
1
1
0
0
31.25 - 87.5
1
1
0
1
62.5 - 175
1
1
1
0
31.25 - 87.5
1
1
1
1
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
TABLE 3B. PLL BYPASS FUNCTION TABLE
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8745BY
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Inputs
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
www.icst.com/products/hiperclocks.html
3
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
÷4
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
REV. B DECEMBER 2, 2004