ICS8745B Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
LAYOUT GUIDELINE
The schematic of the ICS8745B layout example is shown in
Figure 5A. The ICS8745B recommended PCB board layout
for this example is shown in Figure 5B. This layout example
is used as a general guideline. The layout in the actual sys-
tem will depend on the selected component types, the den-
sity of the components, the density of the traces, and the
stack up of the P.C. board.
VDD
SP = Space (i.e. not intstalled)
RU2 RU3 RU4 RU5 RU6 RU7
SP
1K
1K
SP
1K
SP
CLK_SEL
PLL_SEL
SEL0
SEL1
SEL2
SEL3
VDDA
C11
0.01u
R7 VDD
10
C16
10u
(77.76 MHz) ^{Zo = 50 Ohm}
RD2 RD3 RD4 RD5 RD6 RD7
1K
SP
SP
1K
SP
1K
VDD
VDDO
Zo = 50 Ohm
+
R4
100
-
LVDS_input
3.3V
(155.5 MHz)
Zo = 50 Ohm
SEL0
SEL1
Zo = 50 Ohm
3.3V PECL Driver
CLK_SEL
R8A R9
50
50
R10
50
SEL2
U3
1
2
3
SEL0
SEL1
4
5
6
7
8
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
8745
Q3
nQ3
24
23
22
VDDO
Q2
nQ2
GND
21
20
19
18
Q1
nQ1
17
VDD=3.3V
VDDO=3.3V
SEL[3:0] = 0101,
Divide by 2
R2
Decoupling capacitor located near the power pins
100
(U1-9) VDD (U1-32)
(U1-22) VDDO (U1-28) (U1-16)
C1
0.1uF
C6
0.1uF
C4
0.1uF
C5
0.1uF
C2
0.1uF
FIGURE 5A. ICS8745B LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
8745BY
www.icst.com/products/hiperclocks.html
10
REV. B DECEMBER 2, 2004