ICS8745B Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V
Power Supply
Float GND
+
-
LVDS
SCOPE
Qx
nQx
V_DD
nCLK0,
nCLK1
V
PP
CLK0,
CLK1
GND
Cross Points
V
CMR
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLK0,
nCLK1
CLK0,
CLK1
nFB_IN
FB_IN
➤ t (Ø)
V_OH
V_OL
V_OH
V_OL
nQx
Qx
nQy
Qy
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t (Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
t sk(o)
PHASE JITTER AND STATIC PHASE OFFSET
OUTPUT SKEW
nQ0:nQ4
Q0:Q4
tcycle n
➤
tcycle n+1
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
Clock _20%
Outputs
80%
t_R
80%
t_F
V_OD
20%
CYLE-TO-CYCLE JITTER
8745BY
OUTPUT RISE/FALL TIME
www.icst.com/products/hiperclocks.html
6
REV. B DECEMBER 2, 2004