ICS8745B Datasheet, PDF (13/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
8745BY
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
MINIMUM
NOMINAL
N
32
A
--
--
A1
0.05
--
A2
1.35
1.40
b
0.30
0.37
c
0.09
--
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
θ
0°
--
ccc
--
--
Reference Document: JEDEC Publication 95, MS-026
www.icst.com/products/hiperclocks.html
13
MAXIMUM
1.60
0.15
1.45
0.45
0.20
0.75
7°
0.10
REV. B DECEMBER 2, 2004