ICS8745B Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1
SEL0 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
2
SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
3
CLK0 Input Pulldown Non-inverting differential clock input.
4
nCLK0 Input Pullup Inverting differential clock input.
5
CLK1 Input Pulldown Non-inverting differential clock input.
6
7
8
9, 32
10
nCLK1
CLK_SEL
MR
V_DD
nFB_IN
Input
Input
Input
Power
Input
Pullup
Pulldown
Pulldown
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
11
FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
12
SEL2 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
13, 19, 25 GND Power
Power supply ground.
14, 15 nQ0, Q0 Output
Differential output pair. LVDS interface levels.
16, 22, 28
V_DDO
Power
17, 18 nQ1, Q1 Output
Output supply pins.
Differential output pair. LVDS interface levels.
20, 21 nQ2, Q2 Output
Differential output pair. LVDS interface levels.
23, 24 nQ3, Q3 Output
Differential output pair. LVDS interface levels.
26, 27 nQ4, Q4 Output
Differential output pair. LVDS interface levels.
29
SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
30
V_DDA
Power
Analog supply pin.
31
PLL_SEL Input
Pullup
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8745BY
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2
REV. B DECEMBER 2, 2004