ICS8745B Datasheet, PDF (11/15 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V_DDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have same
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
R7 C16 C11
C5
C6
U1
Pin 1
C4
GND
VDDO
VDD
VDDA
C1
C2
VIA
50 Ohm
Traces
8745BY
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8745B
www.icst.com/products/hiperclocks.html
11
REV. B DECEMBER 2, 2004