IC-TW2_13 Datasheet, PDF (6/28 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = VDDA = 3.0...5.5 V, Tj = -40...125 °C, unless otherwise stated
Item Symbol Parameter
No.
Conditions
Digital Inputs NRST
501 Vt()hi
Input Threshold Voltage hi
VDD = 3.3 V +/- 10 %
VDD = 5.0 V +/- 10 %
502 Vt()lo
Input Threshold Voltage lo
VDD = 3.3 V +/- 10 %
VDD = 5.0 V +/- 10 %
503 Ipu()
Input Pull-up Current
V() = 0...VDD - 1 V
504 Vpu()
Input Pull-up Voltage
Vpu() = VDD - V(), I() = -3 µA
Digital Inputs CLKSEL, CLKEXT
601 Vt()hi
Input Threshold Voltage hi
VDD = 3.3 V +/- 10 %
VDD = 5.0 V +/- 10 %
602 Vt()lo
Input Threshold Voltage lo
VDD = 3.3 V +/- 10 %
VDD = 5.0 V +/- 10 %
603 Ipd()
Input Pull-down Current
V() = 1 V...VDD
604 Vpd()
Input Pull-down Voltage
I() = 3 µA
Digital Outputs A_U, NA_NU, B_V, NB_NV, Z_W, NZ_NW
701 Vs()hi
Output Saturation Voltage hi
Vs()hi = V(VDD) - V(), I() = -6 mA;
VDD = 3.3 V +/- 10 %
VDD = 5.0 V +/- 10 %
702 Isc()hi
Short-circuit Current hi
V() = GND
703 Vs()lo
Output Saturation Voltage lo
I() = 6 mA;
VDD = 3.3 V +/- 10 %
VDD = 5.0 V +/- 10 %
704 Isc()lo
Short-circuit Current lo
V() = VDD
705 tr()
Output Rise time
VDD = 3.0 V, CL() = 10 pF
706 tf()
Output Fall Time
VDD = 3.0 V, CL() = 10 pF
707 I()max
Permissible Load Current
source and sink
708 twhi
Duty Cycle at Output A, B
referred to period T, see Fig. 1
709 tAB
Output Phase A vs. B
referred to period T, see Fig. 1
710 tMTD
Minimum Transition Distance see Fig. 1
Signal Processing
801 AAabs Absolute Angular Accuracy
referred to 360° input signal
GC(2:0) = 1
INTER(7:0) = 0
FREQ(6:0) = 127
f() < 50 Hz
802 AArel
Relative Angular Accuracy
referred to period of A, B
GC(2:0) = 1
INTER(7:0) = 0
FREQ(6:0) = 127
f() < 50 Hz
803 ABrel
Relative Angular Accuracy
A vs. B
Index Comparator PINZ, NINZ
901 Vin()sig Permissible Input Voltage Range
902 Vin()os Input Referred Offset Voltage
903 Vin()step Comparator Offset Step Size
OFSZ = 0..7
OFSZ = 8..15
Power-Down-Reset
A01 VDDon
Turn-on Threshold VDD
(power on release)
A02 tbusy()cfg Duration of Startup Configuration
Rev E2, Page 6/28
Unit
Min. Typ. Max.
1.5
V
3.3
V
0.8
V
1.0
V
-3
µA
500 mV
1.5
V
3.3
V
0.8
V
1.0
V
4
µA
500 mV
-100
0.5
V
0.4
V
-15 mA
0.3
V
0.25
V
20
140 mA
4
ns
4
ns
-10
10
mA
50
%
25
%
1/ fcore
-6
6
DEG
-20
20
%
1/2
%
AArel
0.0
VDD
V
-15
+15 mV
1.5
mV
-1.5
mV
1.8
V
20
ms