IC-TW2_13 Datasheet, PDF (23/28 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
2W-Interface timing
The timing of the 2W-Interface is dependent on the
type of access performed. Register bank access and
EEPROM write access can be performed at full speed.
EEPROM read access requires a slow SCLK. Also a
20 ms delay is required after every EEPROM write ac-
cess before a new transaction of any kind is started
(this includes read and write to the register bank).
t
SCLKhigh
Rev E2, Page 23/28
t
SCLKlow
t
t
SDATset SDAThold
DATA WRITE
t
SCLK2SDAT
t
SCLK2SDAT
DATA READ
Figure 18: 2W-Interface timing diagram
2W-Interface timing
Parameter Description
Condition
t_SCLKhigh SCLK high
EEPROM read access
Any other access
t_SCLKlow SCLK low
EEPROM read access
Any other access
t_SDATset
SDAT setup before falling edge of
SCLK
Write access
t_SDAThold SDAT hold after falling edge of
SCLK
Write access
t_SCLK2SDAT SCLK to SDAT valid delay
after rising edge of SCLK
EEPROM read access
Any other access
Notes
Timings given above are valid for f_osc = 20 MHz and scale with f_osc.
For instance, f_osc = 22 MHz reduces all given timings by 10%.
min
8 µs
400 ns
8 µs
400 ns
100 ns
100 ns
5 ns
5 ns
max
7µs
105 ns
Table 32: 2W-Interface timing
Trouble Shooting
To transfer iC-TW2’s configuration data from RAM to
EEPROM command EE_WRITE must be used.
Power must be available over the whole process taking
approx. 100 ms. The suggested 1 µF bypass capaci-
tors are important. GUI button <Read EPPROM> must
deliver reliable contents.
To help iC-TW2’s 2-wire interface not to receive distur-
bances, an external pull-down resistor at SCLK (e.g.
1 kΩ) may be used to support its internal pull-down
keeping the idle state.
iC-TW2’s interface does not feature a timeout, and
there is no enable pin (as for SPI). A certain risk for
loosing the synchronisation does exist. For instance,
connecting a programming cable may introduce edges
to SCLK, so that the interface is not synchronized for
communication anymore.
In case of communication problems try to reset iC-TW2
by pulling pin NRST low. When doing so, there should
be no communication.
Another solution can be to clear the interface by ap-
plying approx. 50 clock pulses to SCLK while SDAT is
held low.