IC-TW2_13 Datasheet, PDF (22/28 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
SCLK
Rev E2, Page 22/28
SDAT
1
1
0
0 a2 a1 a0
d31 d30
d0
0
0
1
SDAT is sampled on
falling edge of SCLK
3 bit address
32 bit data
SDAT is driven externally
SDAT is driven by iC-TW2
extra clocks before
new access
Figure 17: EEPROM read access on 2-wire interface
new access
The 3 bit address a(2:0) selects the EEPROM register
to write to (Figure 13). Each EEPROM register is 32
bits wide, therefore 32 data bits d(31:0) are sent across
the interface. At least 20 ms delay is required after ev-
ery transaction before any new access can start.
EEPROM read access is shown in Figure 17. The start
bit is followed with the 4 bit read command 1100 and
the 3 bit address a(2:0). An idle clock cycle is used
to avoid any contention on SDAT while reversing data
flow direction. Finally d(31:0) is shifted out on SDAT.
EEPROM read access is slow.
At least one extra clock with SDAT low is required after
every transaction on the 2-wire interface before a new
access is started. The interface will not work correctly
if this clock cycle is omitted.
Refer to Table 32 regarding timings requirements.
Please note, given timing specifications scale with f_osc.
For instance, with f_osc = 22 MHz timings are reduced by
10%.
EEPROM Commands
c 1 e b Description
0 1 0 0 Erase followed by write
0 1 0 1 Block erase followed by block write
0 1 1 0 Write
0 1 1 1 Block write
1 1 0 0 Read. Please refer to Figure 17 for more details
1 1 0 1 Reserved. Do not use this command
1 1 1 0 Erase
1 1 1 1 Block erase
Purpose
Normal EEPROM programming
Test only
Special production environment
Test only
Test only
Special production environment
Table 31: EEPROM Commands