IC-TW2_13 Datasheet, PDF (19/28 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
START UP
Rev E2, Page 19/28
Power-On-Reset
The iC-TW2 contains a built-in Power-On-Reset (POR)
circuitry. The POR keeps the iC-TW2 in reset as long
as the applied power supply voltage does not allow
reliable operation. Once the power supply ramps up
above 1.8 V, the POR releases the reset and the iC-
TW2 starts the configuration cycle. 20 ms after the de-
vice goes out of reset, normal operation begins.
power supply
ramp-up
reset
True relative
operation, A/B
phase relation to
Z is unknown
A_U
B_V
Z_W
STARTUP(1:0) = 00
A/B has known
phase relation to
Z (same on each
startup)
A_U
B_V
Z_W
Burst output to A_U
absolute position
within period
B_V
Z_W
STARTUP(1:0) = 10
STARTUP(1:0) = 11
RELATIVE
ABSOLUTE
BURST
Volts V
DD
3.3 or 5.0 V
1.8 V
0.0 V
Power- On- Reset releases,
iC-TW2 starts configuration
20 ms
Time
iC-TW2 starts A/B
pulse generation.
Power supply and
sensor input signals
should be stable to
avoid A/B toggling.
Figure 11: Power supply ramp-up
Figure 12: Startup behaviour
STARTUP(1:0) Addr. 0x01; bit 4:3
R/W
Code
Function
00
RELATIVE
A/B output signals are kept low during startup. This
resembles true relative operation since there is no
relationship between A/B levels and sensor position
(and therefore Z output) on startup.
01
Reserved
10
ABSOLUTE
A/B output signals are phase-related to Z output.
A/B output levels are defined by the absolute
sensor position within a period. The register IPOS
can be used to program the desired A/B to Z phase
relationship.
11
BURST
The absolute sensor position within the period is
output by an A/B burst.
To avoid A/B output toggling it is important that the
power supply and the input signals are stable as soon
as normal operation begins. In applications with a
slowly rising power supply, it might be necessary to
connect an external RC reset to pin NRST to prolong
the reset. In applications where startup A/B toggling
is acceptable, no precaution must be taken as the iC-
TW2 will properly power up on an indefinitely slow sup-
ply rise time.
The iC-TW2 startup behaviour is controlled by pro-
gramming the two control bits STARTUP(1:0) in reg-
ister 0x01. Three possible startup configurations are
allowed, shown in Figure 12. The default behaviour
must be specified by the eeprom.
Table 29: Startup sequence selection
Reset
A control bit RESET is provided to block any burst
A/B pulses during chip reconfiguration by a microcon-
troller. While RESET is set A/B/Z output generation is
stopped. Access to the interface and register bank is
not affected.
RESET
Code
0
1
Notes
Addr. 0x01; bit 6
R/W
Function
A/B/Z output according to STARTUP default
A/B/Z output halted following reset
RESET = 1 may be programmed to the EEPROM or
can be used temporarily to avoid spurious A/B/Z
output pulses when reconfiguration by an external
microcontroller is intended.
Table 30: Restart of interpolation engine following
power-on or software initiated reset.