IC-MB3 Datasheet, PDF (22/26 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER, 1-Chan./3-Slaves

iC-MB3
BiSS INTERFACE MASTER, 1-Chan./3-Slaves
Rev D1, Page 22/26
Initialization (for slaves with BiSS B-Mode register communication)
To initialize the bus subscribers and to allow them to find their position in the queue (and particularly so that the
first slave recognizes its position as such) the master line must be set to 0 after a 1 period (longer than the longest
sensor timeout). The slaves themselves signal that initialization has been successful with a 0 on line SL1.
During initialization internal counters and error flags in the master are deleted or set as appropriate. Should a
slave prove faulty and not switch to 0 initialization must be aborted by a BREAK command. Initialization ends
when the CDM timeout flag is set (address 243).
Communication in sensor mode
The transmission of sensor data begins when at pin MA1 the master outputs the clock signal with the clock
frequency selected by FREQ. The line delay, i.e. the transmission propagation until an acknowledgement is
generated at SL1, is determined from the second falling edge onwards.
While the clock continues to be output at MA1 the master waits for the slaves' start bit (1) signaling the start of
data transmission. Following this the actual clocking out of sensor data begins, i.e. the sensors place a new bit
on the SL1 line with each rising edge on the MA1 line.
The sensor data being input into the master and the ensuing sets of CRC data are written to the appropriate
sensor data RAM. At the same time the new CRC value is calculated in accordance with InvSensCRC and using
the CRC polynomial stored in the configuration RAM. Should, after entry of the last CRC bit, the system ascertain
that transmission was faulty the relevant validity message in address 241 is deleted and error message
nSENSERR set in the status register at address 240. At the same time the sensor data RAM banks are swapped.
Register communication in BiSS B-Mode
Once the slaves have signaled their readiness for register communication (SL1 = 0) the addressing sequence is
compiled, consisting of a start bit (1), the slave ID, the register address, the write/read flag, the inverted CRC
calculated from this and a stop bit (0). This sequence is then transmitted bit by bit.
At the same time the ID distribution among the slaves is checked; should none of the slaves react (should SL1
not signal a 1 after 9 clock pulses) communication is aborted and a register error message generated (nREGERR
= 0). The same happens if the slave response is not 0 after the 17^th rising edge at MA1.
If a register value is to be transmitted to a slave transmission of the new register value begins after 17 clock
pulses (i.e. following the transmission of the start bit, slave ID, register address, WNR, CRC and stop bit). This
new register value consists of a start bit (1), the new contents of the register, the inverted CRC code and a stop
bit (0). At the same time the slave response (SL1) is checked. If the slave does not send a start bit for any reason
(if the register addressed does not exist, for example, or access to a write protected register is attempted)
communication is aborted after 4,096 MA1 clock pulses and the message nWDERR generated; a register error
(nREGERR = 0) is signaled if the CRC proves faulty.
If transmission has proved free of error further register values are then compiled as needed and transmitted until
communication with the register has ended. If no errors have occurred during communication register 243 then
has a value of 0; in the event of error this value is the number of bytes transmitted correctly.
When reading out a register value from a slave, following a correct addressing sequence (see above) the system
waits while the clock pulse continues to be output at MA1 until the addressed slave sends a start bit. During this
waiting period a slave can read out a connected EEPROM, for example, and then transmit this value to the
master. Once the slave's start bit has been entered into the master the actual data bits are stored and the CRC
carried out on the fly. This cyclic redundancy check operates with the fixed polynomial 10011b and with inverted
CRC bits. Should a CRC error occur during transmission this is signaled by a register error; the number of register
values transmitted without error is stored in register 243 and further communication aborted.
If no errors occur during the transmission of data the next register values can be transmitted from the slave to the
master by continued clock pulses at MA1. Register 243 contains a 0 if transmission has proved error free.