IC-MB3 Datasheet, PDF (10/26 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER, 1-Chan./3-Slaves

iC-MB3
BiSS INTERFACE MASTER, 1-Chan./3-Slaves
Rev D1, Page 10/26
OPERATING REQUIREMENTS: BiSS Interface
Operating conditions: Register bit SELSSI = 0
VDD = 3 ... 5.5 V, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item Symbol Parameter
Conditions
Fig.
Min.
Unit
Max.
Sensor Mode
l60 TMAS
Clock Period
FreqSens via FREQ(4:0) selected in
8
accordance with table on page 17
l61 tMASl
Clock Signal Lo Level Duration
8
l62 tMASh Clock Signal Hi Level Duration
8
l63 tpLine
Permissible Line Delay
8
l64 ªtpL
Permissible Propagation Delay of
ªtpL = max(|tpLine - tpLx|); x= 1 ... n
8
Subsequent Clock Cycles vs. 1^st
Clock Cycle
l65 Ttos
Permissible Timeout (Slave)
8
Register Mode*
l65 TMAR
Clock Period
FreqReg via FREQ(7:5) selected in
9
accordance with table on page 17
l66 tMA0h
“Logic 0" Hi Level Duration
9
l67 tMA1h
“Logic 1" Hi Level Duration
9
l68 tMAth
Clock Signal Hi Level Duration
register data readout
9
l69 tsSL
Setup Time:
9
SL1 stable before MA1 lo6hi
l70 thSL
Hold Time:
9
SL1 stable before MA1 lo6hi
2
320 1/f(CLK)
50
% TMAS
50
% TMAS
0
indefinite
25
% TMAS
55
% TMAS
2
256
25
75
50
30
20
TMAS
% TMAR
% TMAR
% TMAR
ns
ns
l71 Ttor
Permissible Timeout (Slave)
9
80
% TMAR
*) For clocking to occur in register mode the slaves must have signaled that they are ready for register mode communication (see page 17).
Figure 8: Timing diagram of sensor mode
Figure 9: Timing diagram of register mode
Evaluating SL1 Signals
In BiSS mode delay times of longer than one clock cycle are permissible, with the result that line delays during
communication are negligible. Evaluation of the sensor response is delayed until the first falling edge at SL1 while
at MA1 the clock signal continues to be output.
Within one MA1 clock cycle four equally distributed sampling instances are available. Following the falling edge
at SL1, the slave's acknowledge signal, the SL1 level is evaluated two sampling instances on, close to the center
of the transmitted bit.