IC-MB3 Datasheet, PDF (12/26 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER, 1-Chan./3-Slaves

iC-MB3
BiSS INTERFACE MASTER, 1-Chan./3-Slaves
DESCRIPTION OF FUNCTIONS
iC-MB3 must be configured in accordance with the
sensors connected to it; to this end a special area of
memory has been included in the device. The other
memory banks are used for the interim storage of
incoming slave data or of slave data yet to be
transmitted.
iC-MB3's second main component is its logic blocks
which enable communication with the controller and
generate the BiSS interface protocol on the slave side
of the chip.
Microcontroller Interface
Via pins CFGSPI and INT_NMOT iC-MB3 can be
configured for operation with an SPI-competent
microcontroller, an Intel 8051 controller or a 68HC11
Motorola controller.
Here, 8-bit multiplex mode is used, in which the
bidirectional data bus alternately transmits addresses
and data in blocks of 8 bits (see Figures 3 to 6).
Rev D1, Page 12/26
Communication Modes
CFGSPI
0
0
1
INT_NMOT
0
1
-
Mode
Motorola 68HC11
Intel 8051
SPI
(polarity= 0, phase= 0)
Figure 11: Wiring diagram for the microcontroller
and iC- MB3.
When operated in conjunction with an SPI controller pin ALE is used as a clock input (SCK) and pin NCS as an
enable input (NCS), with DB0 as the data input (SI) and DB1 as the data output (SO). Data is transmitted serially
in successive blocks of 8 bits (command, address and data).
Four commands are available. These are WriteData (0000 0010b), ReadData (0000 0011b), ReadStatus (0000
0101b) and WriteInstruction (0000 0111b). The first two commands can be used to write data to or read data from
iC-MB3's registers. The latter two commands are truncated write and read commands where the start address is
fixed (namely that of the command register to address 244 and that of the status register to address 240). This
means that it is not necessary to give an address, with the data directly adhering to the command.
With all commands it is possible to transmit several bytes of data consecutively if the NCS signal is not reset and
ALE/SCK continues to be clocked. The address transmitted (240 for ReadStatus and 244 for WriteInstruction) is
then the start address which is internally increased by 1 following each transmitted byte.