IC-MB3 Datasheet, PDF (20/26 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER, 1-Chan./3-Slaves

iC-MB3
BiSS INTERFACE MASTER, 1-Chan./3-Slaves
Rev D1, Page 20/26
Address 243: Register Messages
Bit Designation
Function
7 CDM TIMEOUT Control data timeout elapsed (1), not elapsed (0)
6 REG
Current register data bit at the slave operating on BiSS model C
5 REGBYTES(5) Not used
4...0 REGBYTES(4:0) Number of register bytes transmitted correctly if an error occurs
Remarks
1
2
3
1. A new control data communication can only be made once the CDM timeout has elapsed; a new CDM data
frame may not be introduced before this time.
2. During the data transmission in BiSS C-Mode protocol, where register data is transmitted together with the
sensor data, the current register data bit can be read out via bit REG. Similar to the sensor data this bit also
has a second storage section which allows the readout of bits transmitted during the last cycle while a new
cycle is running. A swap occurs in parallel with that of the sensor data banks.
3. If no errors occur during transmission these bits are set to 0. Otherwise the number of register bytes
successfully transmitted without error is displayed.
Address 244: Command Register
Bit Designation
Function
7 BREAK
The current action is aborted (e.g. the clock at MA1 is stopped)
6 UCREADSENS RAM bank swapping is blocked
5 SWRAMBANK All RAM banks and the validity message register are forcibly
swapped
4 INIT
The sensor is initialized
3 REGCMD
Executes transmissions of register data
2 GETSENS0
Single request for sensor data with a high cycle termination
(control data bit CDM = 0)
1 GETSENS1
Single request for sensor data with a low cycle termination
(control data bit CDM = 1)
0 AGS
Start of automatic sensor data requests (AutoGetSens)
Remarks
All bits with the exception of AGS, UCREADSENS and SWRAMBANK are independently deleted by the master
once the command has been carried out.
All current actions can be aborted using the BREAK command so that a defined state can be resumed if one of
the sensors proves faulty, for example.
During the readout of more than one sensor data register by the controller it is possible that the RAM banks in the
master could be swapped over once a sensor data transmission is complete. So that the controller only reads
related values bit UCREADSENS should be set at the start of the readout and returned at the end; this
suppresses the RAM swap. With the start of a new sensor data cycle previous values are then overwritten by the
new sensor data.
Each setting or deletion of bit SWRAMBANK forces the sensor data banks to be swapped over. Data just input,
for example, can then be read out if a cycle has ended during UCREADSENS = 1 (this is indicated by EOT in the
status register switching to 1 during the suppression of the RAM swap).