IC-MB3 Datasheet, PDF (17/26 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER, 1-Chan./3-Slaves

iC-MB3
BiSS INTERFACE MASTER, 1-Chan./3-Slaves
Configuration - Master
Master Clock
The master clock, either generated by the basic clock
of the internal 20 MHz oscillator (CLKENI = 1) or by an
external clock oscillator (CLKENI = 0) which supplies
pin CLK, is set with the aid of the frequency division
register (address 230).
The clock frequency for both BiSS sensor and SSI
modes is set via FREQ(4:0) in accordance with the
table on the top right. With an external clock pulse of
f_CLK = 20 MHz clock frequencies ranging from 62.5 kHz
to 10 MHz can thus be selected for sensor data
transmission.
Both BiSS and SSI devices recognize an idle bus at
the end of a transmission cycle via a monoflop timeout
elapsing (timeoutSENS, see BiSS protocol). The
choice of possible clock frequency is thus limited as
the duration of both the high and low level may not
exceed the shortest timeout of all of the connected
subscribers (slaves).
BiSS devices switch to register mode on recognizing
that the bus is idle after a high-low transition at the
clock input and signal this state back to the master on
the data line.
The clock frequency in BiSS register mode is set via
FREQ(7:5) and can lie within a range of ca. 244 Hz to
5 MHz. Here selection is also limited as with the
above; a different monoflop timeout now recognizes
the idle bus at the end of the cycle (timeoutREG, see
BiSS protocol).
Additionally, BiSS devices generally only permit a
lower clock frequency (such as 250 kHz maximum, for
example) because the clock form has to be evaluated
as a PWM signal.
Rev D1, Page 17/26
Master Clock for BiSS Sensor Mode and SSI
(FreqSens)
FREQ(3:0)
FREQ(4) = 0
FREQ(4) = 1
0
f_CLK/2
not permitted
1
f_CLK/4
f_CLK/40
2
f_CLK/6
f_CLK/60
3
f_CLK/8
f_CLK/80
4
f_CLK/10
f_CLK/100
5
f_CLK/12
f_CLK/120
6
f_CLK14
f_CLK140
7
f_CLK/16
f_CLK/160
8
f_CLK/18
f_CLK/180
9
f_CLK/20
f_CLK/200
10
f_CLK/22
f_CLK/220
11
f_CLK/24
f_CLK/240
12
f_CLK/26
f_CLK/260
13
f_CLK/28
f_CLK/280
14
f_CLK/30
f_CLK/300
15
f_CLK/32
f_CLK/320
A combination of FREQ(4) = 1 and FREQ(3:0) = 0 is not permitted;
for a clock frequency of f_CLK/20 FREQ(4) = 0 and FREQ(3:0) = 9
must be set.
Master Clock for BiSS Register Mode
(FreqReg)
FREQ(7:5)
0
1
2
3
4
5
6
7
FreqReg
FreqSens/2
FreqSens/4
FreqSens/8
FreqSens/16
FreqSens/32
FreqSens/64
FreqSens/128
FreqSens/256
Automatic request for sensor data
The frequency with which new requests for sensor
data are sent to the slaves is set using FREQAGS
according to the table on the right. With an external
clock of 20 MHz sensor data request cycles ranging
from 1 µs to 4 ms are possible.
FREQAGS must be set in such a way that the
distance between two requests for data is greater than
a complete cycle; this consists of the transmission of
a request, an acknowledge signal (including any line
delays), a start bit (including process times), a register
bit (optional), the sensor and CRC bits of each slave
and the longest sensor timeout of all the slaves.
Automatic Sensor Data Request
(FreqAGS)
FREQAGS(6:0)
0
1
2
...
125
126
127
FREQAGS(7)= 0
f_CLK/20
f_CLK/40
f_CLK/60
...
f_CLK/2520
f_CLK/2540
f_CLK/2560
FREQAGS(7)= 1
f_CLK/625
f_CLK/1250
f_CLK/1875
...
f_CLK/78750
f_CLK/79375
f_CLK/80000