IC-MB3 Datasheet, PDF (11/26 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER, 1-Chan./3-Slaves

iC-MB3
BiSS INTERFACE MASTER, 1-Chan./3-Slaves
Rev D1, Page 11/26
OPERATING REQUIREMENTS: BiSS Interface (SSI mode)
Operating conditions: Register bit SELSSI = 1;
VDD = 3 ... 5.5 V, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item Symbol Parameter
Conditions
Fig.
l80 TMAS
l81 tMASh
l82 tMASl
l83 tsDC
l83 thDC
Clock Period
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
Setup Time:
SL1 stable before MA1 lo6hi
Hold Time:
SL1 stable before MA1 lo6hi
FreqSens über FREQ(4:0) selected in 10
accordance with table on page 17
10
10
10
10
Min.
2
Max.
320
Unit
1/f(CLK)
50
50
30
%TMAS
%TMAS
ns
10
ns
Figure 10: Timing diagram of SSI mode.
Evaluating SL1 Signals
In BiSS interface SSI mode SL1 values are sampled with the rising edge at MA1. An overall delay of the sensor
response to the clock at MA1, caused by process times in the sensor or transmission times, is permissible up to
the length of one clock cycle.