IC-MSB Datasheet, PDF (18/29 Pages) IC-Haus GmbH – SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

iC-MSB^SAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
INPUT CONFIGURATIONS
Rev D2, Page 18/29
Input Configurations
All input stages are configured as instrumentation am-
plifiers and thus directly suitable for differential input
signals. Referenced input signals can be processed as
an option; in this mode input X2 acts as a reference.
INMODE
Code
0
1
Note
Adr 0x03, bit 2
Function
Differential input signals
Single-ended input signals *
* Input X2 is reference for all inputs.
Table 17: Input Signal Mode
Both current and voltage signals can be processed as
input signals, selected using RIN12(0) and RIN0(0).
In I Mode an input resistor Rin() becomes active at
each input pin, converting the current signal into a volt-
age signal. Input resistance Rin() consists of a pad
wiring resistor and resistor Rui() which is linked to the
adjustable bias voltage source VREFin(). The follow-
ing table shows the possible selections, with Rin() giv-
ing the typical resulting input resistance (see Electri-
cal Characteristics for tolerances). The input resistor
should be set in such a way that intermediate poten-
tials VDC1 and VDC2 lie between 125 mV and 250 mV
(verifiable in Calibration Mode 2).
In V Mode an optional voltage divider can be selected
which reduces unacceptably large input amplitudes to
ca. 25%. The circuitry is equivalent to the resistor
chain in I Mode; the pad wiring resistor is considerably
larger here, however.
RIN12
RIN0
Code
–000
–010
–100
–110
1—1
0—1
Adr 0x0E, bit 3:0
Adr 0x13, bit 3:0
Nominal Rin() Intern Rui()
1.7 kΩ
1.6 kΩ
2.5 kΩ
2.3 kΩ
3.5 kΩ
3.2 kΩ
4.9 kΩ
4.6 kΩ
20 kΩ
5 kΩ
high
impedance
1 MΩ
I/V Mode
current input
current input
current input
current input
voltage input
voltage input
Table 18: I/V Mode and Input Resistance
BIAS12
BIAS0
Code
0
1
Adr 0x0E, bit 6
Adr 0x13, bit 6
VREFin()
Type of sensor
2.5 V)
Lowside sink current (I Mode)
1.5 V)
Highside current source (I Mode)
Table 19: Reference Voltage
BIASEX
Code
0-
10
11
Note
Adr 0x0D, bit 7:6
VREFin()
Signal at X2
internal
Neg. Zero Signal (Index -), input
internal *
Ref. Voltage VREFin12, output
external *
Ref. Voltage VREFin, input
*) The voltage at X2 is reference for all inputs.
Table 20: Input Reference Selection
Figure 2: Input instrumentation amplifier and signal conditioning