IC-MSB Datasheet, PDF (14/29 Pages) IC-Haus GmbH – SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

iC-MSB^SAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
I²C Slave Mode (ENSL = 1)
In this mode iC-MSB behaves like an I²C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MSB’s internal registers.
For chip release verification purposes an identification
value is stored under ROM address 0x1F; a write ac-
cess to this address is not permitted.
CHPREL
Code
0x00
0x04
0x05
0x25
Adr 0x1F, bit 7:0 (ROM)
Chip Release
Not available
iC-MSB ^SAFETY v4
iC-MSB ^SAFETY v5
iC-MSB2 v5
Table 7: Chip Release
NTRI
Code
0
1
Notes
Adr 0x02, bit 7
Function
Output drivers disabled
Setting the operating mode, output drivers active
NTRI is evaluated only during I²C slave mode.
Table 8: Tristate Function And Op. Mode Change
Rev D2, Page 14/29
Register
Address
0x00-0x18
0x19-0x1A
0x1B-0x1E
0x1F
0x20-0x23
0x24-0x37
0x38
0x39-0x3A
0x3B-0x3E
0x3F
0x40-0x43
0x44-0x7F
Read access in I²C slave mode (ENSL = 1)
Content
Configuration: register addresses 0x00-0x18
Not available
OEM data: register addresses 0x1B-0x1E
Chip release (ROM)
Configuration: register addresses 0x20-0x23
Not available
Configuration: register address 0x18
Not available
OEM data: register addresses 0x1B-0x1E
Chip release (ROM)
Current error memory
Not available
Table 9: RAM Read Access
Register
Address
0x00
0x01
0x02
0x03-0x16
0x17
0x18
0x19-0x1A
0x1B-0x1E
others
Write access in I²C slave mode (ENSL = 1)
Access and conditions
Changes possible, no restrictions
Changes possible (wrong entries for CFGIBN can
limit functions)
Bit 7 = 0 (NTRI): changes to bits (6:0) permitted
A change of operating mode follows only on writing
Bit 7 = 1 (NTRI); when doing so changes to bits
(6:0) are not permitted.
Changes possible, no restrictions
Bit 3 = 1 (ENSL):
changes to bits (7:4) and (2:0) permitted
Changes possible, no restrictions
Not available
Changes possible, no restrictions
No changes permitted
Table 10: RAM Write Access